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Learn the machine.
One gate at a time.
Interactive lessons from a single transistor to a full processor. Read for a minute, then prove it in the browser.
Design for Test: Scan, ATPG & Signatures
Making a chip testable after it leaves the fab: scan chains that reach buried flops, stuck-at patterns that catch defects, and MISR signatures that compress the results.
The whole product, at a glance.
NAND is universal
Build AND, OR, and NOT from a single gate. Once you see it, every schematic in your future reads differently.
Every ASIC on your phone is millions of NANDs. Master this and gate-level thinking clicks.
Every skill from the actual job posting, turned into a learning path.
We pull real job descriptions from chip companies, mine every listed skill, and map each one to a topic and a set of problems. No filler chapters, no generic curriculum. If the JD says it, the track teaches it.
SoC Design Engineer
AMD · Markham, ON · Full-time · $128K–$192K
- Lint clean-up on RTL blocks and subsystems
- CDC analysis and resolution across clock domains
- AMBA family experience: AXI, AHB, APB
- Ethernet and high-speed serial (SerDes) datapaths
- TCL / Makefile / Perl flow scripting
- + 12 more requirements
SoC Design Engineer
4 milestones- 1Lint clean-upM2 · SIGNOFFTopic + problems
- 2CDC analysis and resolutionM2 · SIGNOFFTopic + problems
- 3AMBA family: AXI, AHB, APBM3 · SOC INTEGRATIONTopic + problems
- 4Ethernet & digital comms standardsM4 · NETWORKINGTopic + problems
- 5TCL / Makefile / Perl scriptingM2 · SIGNOFFTopic + problems
- + 13 more topics across 4 milestones
Pick a role. Follow the path.
Real JDs from AMD, onsemi, Marvell and NXP, every listed skill turned into a milestone.
SoC Design Engineer
- M1
- M2
- M3
- M4
RTL Design Engineer, PCIe Subsystem
- M1
- M2
- M3
- M4
SoC CAD / EDA Engineer
- M1
- M2
- M3
- M4
Digital IC Designer
- M1
- M2
- M3
- M4
Design Verification Engineer Intern
- M1
- M2
- M3
Digital Verification Engineer Intern
- M1
- M2
Paste a job posting.
Get a course built for it.
Forge is our AI career architect. It reads the JD, picks the lessons, sequences the problems, and hands you a tailored path. Join the waitlist to get in first.
See what Forge will doReserve your spot.
We'll ping you the moment Forge opens. No spam, unsubscribe in one click.
From a single transistor to your own CPU.
Each node unlocks the next. No prerequisites — start where you are.
Runs in the browser
JavaScript, Python and Verilog compile and grade locally. Nothing to install.
Every module ends with a check
Real testbenches, waveforms, verdicts. You know when it works.
Progress you can feel
Streaks, XP and a global leaderboard. Small wins compound.
Be first when we ship the big stuff.
New tracks, new problems, live interview drills. Share your email and we’ll ping you only when we launch something worth your time. No spam, ever.